Printed circuit boards, referred to herein as printed wiring boards (PWB), can contain so-called high speed balanced differential lines, over which “balanced” signals are carried. In such a system, the two lines of a pair of balanced lines must be oriented, sized, and spaced apart from each other such that the characteristic impedance of the total system is at a design impedance. Any deviations from the ideal configuration can deleteriously affect the characteristic impedance of the transmission lines, reducing system performance. Such PWBs may be used in a wide range of applications, including televisions.
Balanced line PWBs, like other PWBs, may require protection from electrostatic surges as might occur when a person touches a TV. Advantageously such PWBs can be provided with electrostatic discharge (ESD) devices. ESD devices typically are electrically connected between individual PWB lines and ground using so-called “traces”, to shunt the energy of an electrical surge to ground. As critically recognized herein, in the case of a PWB that does not have pairs of balanced lines, each line is independent of other lines, and as a consequence it is relatively easy to place an ESD protection device between a line and ground.
In contrast, as recognized by the present invention, in the case of a PWB employing balanced differential line pairs, it can be difficult at best to connect an ESD device between each balanced line and ground without undesirably crossing the traces or without requiring the use of so-called “vias” (through holes to other layers of the PWB). Likewise, on the other (ground) side of the ESD device, electrical connection to ground can be complicated and may also require vias. Furthermore, traces can be seen electrically as a “stub” on the balanced transmission line, which could undesirably affect the impedance of the balanced line, and so the length of any such traces between a line and an ESD device should be kept as short as possible. Thus, the challenge addressed herein is to provide ESD devices in a PWB that has balanced line pairs within the layout constraints of a balanced line PWB.